Current state of the art general purpose processors rely on memory management units (MMU) to provide both memory protection and address translation functions. The most typical memory management units provide a page-oriented architecture, usually fixed around a small number of different page sizes —4 KB only, 4 KB+64 KB, 4 KB+2 MB, etc. Memory management units are very flexible, but they suffer from multiple drawbacks:                Complicated to design and verify.        Variable performance depending on how the memory management unit is implemented. Most of the commonly used implementations can add significant uncertainty to memory system performance.        For best performance, the memory management unit needs to be tightly integrated in the memory hierarchy, preferably at or near the CPU/L1 cache boundary. Once tightly integrated, it is difficult to remove, reducing the flexibility of the architecture to scale to meet cost and performance targets.        A potentially large memory footprint is required for page table entries due to the small page sizes in big systems. For example, it takes 1,048,576 4 KB pages to fully map a 4 GB memory system.        
An additional problem arises with conventional memory management units used in large, multiprocessor systems using 32 bit processor elements. While the logical address place for each processor or each task will still fit into a 32 bit address place, the physical address place of the memory system may exceed the 32 bit range. In this case an address translation unit is required that is capable of producing wider physical addresses than the logical addresses it started with, so that the total physical address space can be larger than the logical address space.